VF48 Manual
by
Chris Pearson
—
last modified
Feb 24, 2010 01:46 AM
Needs rewriting
vf48doc-placeholder.txt
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This file contains various email messages discussing new VF48 features
It needs to be rewritten, summarising the relevant information
============== TIGC/VF48 Requests as of 03/05/2009 01:34 PM ==================
A)* TIGC receive clock from external 20 MHz clock
B)* TIGC distributes this clock to each VF48 (10)
C)* TIGC Sum the pulses of 4 VF48
D)* enable VF48 chip selection for summing
E)* decision+ summing made within 1-2us (time between level0 and
level1 trigger)
F)* TIGC make an OR of all VF48 busy signal and output a NIM (or TTL)
busy signal.
==============================================================================
9April09
Busy was originally vf48-full - changed to not-empty
==============================================================================
23April09
Changed triple-pulsing, late pulses, fixed threshold writing
Do TIGC reset before vf48Rst/ParWrite! ...
As well as the above change, the following needs adding to the frontend to set the summing enable bits - there are 8 bits per group (and 6 groups per vf48) - in this code the 8 bits are all hardcoded to 1, but this can easily be changed to an odb parameter if needed.
in fevme1.cxx:local_vf48_load() just after polarity setting
// Sum_Enable
for (i=0;i<6;i++) {
DWORD pat = vf48_ParameterRead(myvme, base, i, VF48_MBIT1);
pat |= (0xff << 8);
vf48_ParameterWrite(myvme, base, i, VF48_MBIT1, pat);
}
==============================================================================
2July09
input2 is the level-1 trigger which causes the modules to readout - I think you're sending this signal directly to the vf48 though, so it isn't really needed in the tigc.
> What is already the 2nd input going to TIGC.
> Input 1 is the level 0 trigger but what is input 2 already?
The new firmware is EPCS4_vf48212_kO4d_30jun09.pof in ~pienu/packages/firmware.
Frontend parameter Modebit[6]=1 enables the analog sum (instead of the multiplicities).
in the frontend, in Sum-enable part of parameter loading ...
after this line ...
pat |= ( vfs->sum_enable << 8); // acts on bits 0xFF0000
add this one ...
pat |= 0x40; // set 7th bit to send sum to collector
Collector parameter triggerconfig[3]=1 puts the 20Mhz clock on the vf48 AuxOut (instead of the Lixe trigger).
in the frontend, in init_vme_modules...
after this line ...
// vf48_SetAuxTrig(gVme, gVF48Base[i], 1<<2); /* PIENU Trigger */
add this one ...
vf48_SetAuxTrig(gVme, gVF48Base[i] , 1<<3); /* enable clk out */
Also the reset in-between runs for the reprogrammed module should be removed (the reset on frontend_init is still required).
The event number should be automatically reset at the start of each run
==============================================================================
4July09
TIGCSumEnable 6 (0x6)
TigcDisableMask 3711 (0xE7F)
TigcTrigThreshold 20 (0x14) in VF48 ADC channels/64
DisableMask is bitmask for which ports on tigc to disable, the top one is first, and we usually use the lower group of 6, so E7F is all disabled except 1st, 2nd and 3rd in the lower group of 6
SumEnable is bitmask for which vf48 to sum - *the positions are referring only to the lower group of 6 ports* - (so 6 is 2nd and 3rd of this lower set)
(These two parameters do not really have consistent meanings)
TrigThreshold is in adc-units/64
==============================================================================
8July09
KO4 is konstantins firmware V212 with VME speed improvements and latest reset modifications (KO2 was the first working V212, KO3 had some vme speed improvements)
KO4b is the above KO4, with Analog summing and TIGc connection
KO4c has also the clock out
KO4d has also chris Ohlman triggerLogic and event-number reset
KO4d should have clock-out - but this needs selecting by writing a register, otherwise you get the Ohlman trigger out.
Chris
I checked the files, and firmware KO4c has the correct date, so should be the correct file, if this was flashed (and not some other file), the only reason I can see for the missing clock-out signal, is a bad cable or attaching to the wrong connector - or the module has no clock - the rj45 cable needs to be attached and the jumpers set correctly.
==============================================================================
25Aug09
Yes, 0x80 in modebits1 will enable the summing, and the thresholds will need to be doubled.
Chris
Renee Poutissou wrote:
> This message is mainly for Chris.
>
> I would like to implement the new option in the fevme code but
> I do not have enough details.
> When I look at the web page, I see
> EPCS4_vf48_212ko4f_18aug09.pof
> by Chris Pearson %Gâ%@ last modified Aug 18, 2009 10:45 PM
>
> Raw data supression applies threshold to sum of adjacent channels
> (if enabled with modebits[7])
>
> Does this mean that the way to set this option is to set the
> bit #7 (ie 0x80) of the parameter called VF48_MBIT1 ???
> And, I assume that the "threshold" is the parameter called
> HitThreshold - when the option is set, I assume that this
> threshold must be set higher since it is comparing to the sum
> of two channels, correct?
==============================================================================
Nov09
Fixed TIGC Summing problems
==============================================================================
11Feb10
I don't know why the efficiency seems to vary?
--------------------------------------------------------------
Raw data Suppress - completely suppresses the waveform readout for all channels and all triggers (the evaluated pulse-height and time are still read - however the pulseheight algorithm doesn't work for your pulses).
Channel suppress enable is the mode we use, which only suppresses raw data if there is no pulse.
The threshold for suppression is done on the slope of the signal - if the signal changes by more than the threshold in 3 clocks (effectively the pedestal is subtracted from ~48ns before)
--------------------------------------------------------------
The Problems with the TIGC were ...
The bug in the trigger timeout counter - the counter ran continuously and if the trigger came when it had reached the timeout value, the trigger timed-out immediately. This was fixed by only counting when the trigger had come.
Fixing this didn't solve the inefficiency ...
We found the pedestal problem - the pedestal was taken 1.5us before peak - we changed this to a proper gated-baseline follower, which had the correct behaviour.
This also didn't solve the efficiency problem.
Finally we found the trigger-signal was being missed as it is not synchronised with the TIGC clock - originally the trigger signal was several clocks long so this didn't matter, but then we shortened it to 1 clock due to retriggering, and now it must be correctly re-synchronised to the TIGC clock, or it will be missed (~4% of the time).
=============================================================================
=============================================================================
VF48 VME Addresses
VF48_MAX_CHANNELS DWORD 48
VF48_CSR_REG_RW 0 /**< -RW-D16/32 */
VF48_SELECTIVE_SET_W 0x0010
VF48_SELECTIVE_CLR_W 0x0014
VF48_TEST_REG_RW 0x0020
VF48_FIRMWARE_R 0x0030 /**< -R-D16/32 */
VF48_SOFT_RESET_W 0x0040 /**< Same as NIM -W-D16/32 */
VF48_PARAM_DATA_RW 0x0050 /**< -RW-D16/32 */
VF48_PARAM_ID_W 0x0060 /**< -W-D16/32 */
VF48_SOFT_TRIG_W 0x0080
VF48_GRP_REG_RW 0x0090
VF48_GLOBAL_RESET_W 0x00B0 /**< -W */
VF48_GROUP_ID_RW 0x00C0 /**< -RW */
VF48_GROUP_COINC_RW 0x00C4 /**< -RW */
VF48_GROUP_MULT02_RW 0x00C8 /**< -RW */
VF48_GROUP_MULT35_RW 0x00D0 /**< -RW */
VF48_NFRAME_R 0x00A0 /**< -R-D16/32 */
VF48_DATA_FIFO_R 0x1000 /**< -R-D32 */
/* ================= Parameter IDs for Frontend ======================== */
#define VF48_GRP_OFFSET (DWORD) (12)
#define VF48_PARMA_BIT_RD (DWORD) (0x80)
#define VF48_PEDESTAL (DWORD) (1) //** 0x0000
#define VF48_HIT_THRESHOLD (DWORD) (2) //** 0x000A
#define VF48_CLIP_DELAY (DWORD) (3) //** 0x0028
#define VF48_PRE_TRIGGER (DWORD) (4) //** 0x0020
#define VF48_SEGMENT_SIZE (DWORD) (5) //** 0x0100
#define VF48_K_COEF (DWORD) (6) //** 0x0190
#define VF48_L_COEF (DWORD) (7) //** 0x0200
#define VF48_M_COEF (DWORD) (8) //** 0x1000
#define VF48_DELAY_A (DWORD) (9) //** 0x0005
#define VF48_MBIT1 (DWORD) (10) //** 0x0000
#define VF48_DELAY_B (DWORD) (11) //** 0x0001
#define VF48_LATENCY (DWORD) (12) //** 0x0005
#define VF48_FIRMWARE_ID (DWORD) (13) //** 0x0100
#define VF48_ATTENUATOR (DWORD) (14) //** 0x0190
#define VF48_TRIG_THRESHOLD (DWORD) (15) //** 0x0050
// #define VF48_ACTIVE_CH_MASK (DWORD) (16) //** 0x00FF
// #define VF48_MBIT2 (DWORD) (17) //** 0x0000
#define VF48_ACTIVE_CH_MASK (DWORD) (9) //** 0x00FF << Temporary
#define VF48_MBIT2 (DWORD) (11) //** 0x0000 << Temporary
/* ============================ CSR Bits ============================== */
/*
CSR setting:
0: Run 0:stop, 1:start
1: Parameter ID ready
2: Parameter Data ready
3: Event Fifo Not empty
*/
#define VF48_CSR_START_ACQ (DWORD) (0x00000001)
#define VF48_CSR_PARM_ID_RDY (DWORD) (0x00000002)
#define VF48_CSR_PARM_DATA_RDY (DWORD) (0x00000004)
#define VF48_CSR_FE_NOTEMPTY (DWORD) (0x00000008)
#define VF48_CSR_CRC_ERROR (DWORD) (0x00000020)
#define VF48_CSR_EXT_TRIGGER (DWORD) (0x00000080)
#define VF48_CSR_FE_FULL (DWORD) (0x00008000)
#define VF48_RAW_DISABLE 0x2
#define VF48_CH_SUPPRESS_ENABLE 0x1
#define VF48_INVERSE_SIGNAL 0x8
#define VF48_ALL_CHANNELS_ACTIVE 0xFF
#define VF48_G02 1
#define VF48_G35 2
/* Header definition */
#define VF48_HEADER (DWORD) (0x80000000)
#define VF48_TIME_STAMP (DWORD) (0xA0000000)
#define VF48_CHANNEL (DWORD) (0xC0000000)
#define VF48_DATA (DWORD) (0x00000000)
#define VF48_CFD_FEATURE (DWORD) (0x40000000)
#define VF48_Q_FEATURE (DWORD) (0x50000000)
#define VF48_TRAILER (DWORD) (0xE0000000)
//#define VF48_OUT_OF_SYNC (DWORD) (0x88000000)
//#define VF48_TIMEOUT (DWORD) (0x10000000)
/*
Parameter frame
15 ... ...
CCCCDDDD RVPP PPPP
C: Destination Card/Port N/A
R: Read bit (0:Write, 1:Read)
D: Destination channels (0..5)
bit 11..8
0: channel 1..8
1: channel 9..16
2: channel 17..24
3: channel 25..32
4: channel 33..40
5: channel 41..48
6: channel N/C
7..15: channel N/C
V: Version 0 for now (0:D16, 1:D32(extended))
P: Parameter ID
Default values for the different PIDs
ID# Def Value
1 0x0000 Pedestal
2 0x000A Hit Det Threshold
3 0x0028 Clip Delay
4 0x0020 Pre-Trigger
5 0x0100 Segment size
6 0x0190 K-coeff
7 0x0200 L-coeff
8 0x1000 M-coeff
9 0x0005 Feature Delay A
10 0x0000 Mbit1
0x1: Data simulation
0x2: Supress Raw Data
0x8: Inverse Signal
11 0x0001 Feature Delay B
12 0x0005 Latency
13 0x0100 Firmware ID
14 0x0190 Attenuator
15 0x0050 Trigger threshold
16 0x00FF Active Channel Mask
17 0x0000 Mbit2
0x1: Enable Channel Suppress
0xff00: sampling divisor // Temporary
*/
int vf48_Setup(MVME_INTERFACE *mvme, DWORD base, int mode);
int vf48_EventRead(MVME_INTERFACE *myvme, DWORD base, DWORD *event, int *elements);
int vf48_EventRead64(MVME_INTERFACE *myvme, DWORD base, DWORD *event, int *elements);
int vf48_GroupRead(MVME_INTERFACE *myvme, DWORD base, DWORD *event, int grp, int *elements);
int vf48_DataRead(MVME_INTERFACE *myvme, DWORD base, DWORD *event, int *elements);
int vf48_ExtTrgSet(MVME_INTERFACE *myvme, DWORD base);
int vf48_ExtTrgClr(MVME_INTERFACE *myvme, DWORD base);
void vf48_Reset(MVME_INTERFACE *myvme, DWORD base);
void vf48_SoftReset(MVME_INTERFACE *mvme, DWORD base);
int vf48_AcqStart(MVME_INTERFACE *myvme, DWORD base);
int vf48_AcqStop(MVME_INTERFACE *myvme, DWORD base);
int vf48_NFrameRead(MVME_INTERFACE *myvme, DWORD base);
int vf48_CsrRead(MVME_INTERFACE *myvme, DWORD base);
int vf48_GrpRead(MVME_INTERFACE *myvme, DWORD base);
int vf48_FeFull(MVME_INTERFACE *myvme, DWORD base);
int vf48_EvtEmpty(MVME_INTERFACE *myvme, DWORD base);
int vf48_GrpEnable(MVME_INTERFACE *myvme, DWORD base, int grpbit);
int vf48_GrpRead(MVME_INTERFACE *myvme, DWORD base);
int vf48_GrpOperationMode(MVME_INTERFACE *myvme, DWORD base, int grp, int opmode);
int vf48_ParameterRead(MVME_INTERFACE *myvme, DWORD base, int grp, int param);
int vf48_ParameterWrite(MVME_INTERFACE *myvme, DWORD base, int grp, int param, int value);
int vf48_ParameterCheck(MVME_INTERFACE *myvme, DWORD base, int what);
int vf48_SegmentSizeSet(MVME_INTERFACE *mvme, DWORD base, DWORD size);
int vf48_SegmentSizeRead(MVME_INTERFACE *mvme, DWORD base, int grp);
int vf48_TrgThresholdSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size);
int vf48_TrgThresholdRead(MVME_INTERFACE *mvme, DWORD base, int grp);
int vf48_HitThresholdSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size);
int vf48_HitThresholdRead(MVME_INTERFACE *mvme, DWORD base, int grp);
int vf48_ActiveChMaskSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size);
int vf48_ActiveChMaskRead(MVME_INTERFACE *mvme, DWORD base, int grp);
int vf48_RawDataSuppSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size);
int vf48_RawDataSuppRead(MVME_INTERFACE *mvme, DWORD base, int grp);
int vf48_ChSuppSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size);
int vf48_ChSuppRead(MVME_INTERFACE *mvme, DWORD base, int grp);
int vf48_DivisorWrite(MVME_INTERFACE *mvme, DWORD base, DWORD size);
int vf48_DivisorRead(MVME_INTERFACE *mvme, DWORD base, int grp);
int vf48_MultGroupIDRead(MVME_INTERFACE *mvme, DWORD base);
int vf48_MultGroupIDWrite(MVME_INTERFACE *mvme, DWORD base, int gid);
int vf48_MultGroupCoincRead(MVME_INTERFACE *mvme, DWORD base);
int vf48_MultGroupCoincWrite(MVME_INTERFACE *mvme, DWORD base, int coinc);
int vf48_MultiplicityRead(MVME_INTERFACE *mvme, DWORD base, int which);
int vf48_MultiplicityWrite(MVME_INTERFACE *mvme, DWORD base, int which, int mxx);
int vf48_SetTigcSumEnable(MVME_INTERFACE *, DWORD, int);
int vf48_SetTigcTrigThreshold(MVME_INTERFACE *, DWORD, int);
int vf48_SetTigcDisableMask(MVME_INTERFACE *, DWORD, int);
int vf48_SetTigcSumGains(MVME_INTERFACE *, DWORD, int);
int vf48_TigcGenReset(MVME_INTERFACE *, DWORD);
int vf48_SetAuxTrig(MVME_INTERFACE *mvme, DWORD base, int value);
#endif
