notes.txt

File contents

     V680 Microengine - TRIUMF modification for uSR

The standard V680 TDC generates 48 bits of timing information for 
all inputs for every gate. The uSR experiment requires only 19 bits of
timing information, and events are only valid when one and one only channel 
is hit. The microengine buffers this information to reduce system deadtime, 
presents a flag to the host computer when a valid hit has occurred,
and automatically resets and re-arms the input channels when bad events occur
without host intervention.


Operation:

The Hit and Double Hit flags for all 9 channels are taken to to the logical
block "ONLY1". If one and one only Hit flag is true, and no Double Hit flags
are true, then the signal "OK" is true, else false. If true, the ordinate
of the Hit flag is encoded in the signals Z[2:0]  (See 22a683t sheet 8).


Microengine operation is enabled by the signal "UEN" which is set by
writing Register 4 bit 10. Since the data path is acquired by the microengine
when running, it is not possible to clear this bit in the normal way. Instead,
any write operation to register 8 (the reset register) clears UEN; the
data is ignored.

When the microengine is enabled, an incoming gate generates the internal 
Gate Falls signal "GF". This signal is delayed sequentially in a shift 
register clocked by the 10MHz system clock and used for timing purposes.
Successive time steps are generated called "ST1", "ST2" .. "ST5".

A signal "AE" Actel Enable is set by GF and used to enable microengine
control of the Actel chip register selects (22a683t sheet 6). AE is cleared
at the completion of a microengine cycle. If a previous event has not been
read and cleared (F15 is still set), the new cycle is inhibited.

AE controls a number of multiplexers and latches (22a683t sheet 6,8,9).
The valid Hit ordinate is latched as LZ[2:0] and used as the channel select
input to the Actel chip. During time steps ST1, ST2 the least significant
16 bits of time data are transferred from the Actel chip and latched
at the end of ST2 (22a683t sheet 6,9) into Register 15. During time steps
ST3,4 the next 3 bits of timing data are transferred from the Actel chip, 
together with the channel number (LZ) and the AUX1 auxiliary input,
and latched at the end of ST4 (22a683t sheet 9).

A reset signal ZAP is generated at time ST2, which is used to reset the 
hit registers in preparation for another event (external signal ZAPALL).
Since the ADCs are pipelined, sufficient time remains to digitize the 
previous event during the remaining time steps.

If there is a valid event, the signal Flag 15 "F15" is generated. This 
drives data bit 15 of VME directly through the open-collector driver U8C
during a VME read cycle, bypassing the data path which belongs to the 
microengine. The host may thus poll Register 16 bit 15 (or in fact any 
register 16-31, since the address is not fully decoded). (22a683t sheet 8)

For debugging purposes, several internal signals GF, ST1, AE etc. are
taken via a multiplexer to the control chip testpoint (pin 11, TP1).
Three Vector bits from Register 3 control the multiplexer (22a683t sheet 7).

A couple of minor changes are made in the VMEchip (22a682t sheet 2).
The READ period is extended to allow reading Flag 15 without additional
latching, and the Output Enable signal is extended to registers 16-31.


Andrew Daviel, TRIUMF, October 1998 <advax@triumf.ca>