1 March 2012 sources + binary

by Chris Pearson — last modified Nov 16, 2012 05:34 PM

Fixed vme timing for GefVme Bridge (DS* fall at same time as AS - was too soon for data drivers to turn on) Ext clock done properly with proper recync between ppg and rest of system. Proper PPG/CSR reset added (in place of slow clock selection). Programmable PLL reconfiguration added to allow use of any frequency external clock.